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| Overview |
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SeaSolve’s Mobile WiMAX CTC decoder Core performs duo binary turbo decoding of channel data as per IEEE 802.16e/d specification. The decoder uses MAX LOG MAP Algorithm for decoding.
The CTC decoder is capable of achieving a high throughput encode data rate in the slowest speed FPGA also. |
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Fully synthesizable code |
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Supports all interleaver block sizes of the CTC OFDMA PHY mode including the HARQ and IR HARQ modes: 24, 36, 48, 72, 96, |
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108, 120, 144, 180, 192, 216, 240, 480, 960, 1440, 1920, and 2400 pairs. |
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Programmable number of iterations dynamically changeable per block. |
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Performs parallel processing with parameterizable number of SISOs to achieve high throughput and reduce latency |
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Latency depends on block size |
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clk
rst
new_block
no_iter
n_size
a
b
y1
w1
y2
w2
new_data
hard_bits
finished
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: in std_logic;
: in std_logic;
: is a pulse;
: is a 3 bit input which reads 0 to 7
: takes the size of the input
: input a
: input a
: input a
: input a
: input a
: input a
: is a valid_out
: output data
: is a done signal
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| Inputs |
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| Outputs |
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| Deliverables |
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The Core is delivered as a synthesized netlist (FPGA) or RTL VHDL for ASIC. The
Core package contains: |
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RTL-model library for simulation (ModelSim) |
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stand-alone test bench (VHDL)
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complete documentation and technical support for integration |
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