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Code word length (n) = 204 symbols |
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Message length (k) = 188 symbols |
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Error correcting capability(t) = 8 symbols. |
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Symbol size(m) = 8 bits. |
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Field polynomial f(x) = x8 + x4 +x3 + x2 + 1 |
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Generator polynomial g(x) = (x + a0)(x +a1)…………….(x +a(2t – 1)) |
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No of syndromes = 16. |
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Fully synchronous design using a single clock. |
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Counts Flags failure if the number of errors is more than correctable errors. |
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8-bit symbol size. |
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Indicate the first byte of each codeword. |
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325 clocks latency. |
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Processing delay 204 cycles per codeword (1 cycle per symbol). |
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Infinite length continuity. |
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Fully synthesizable VHDL code |
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Fully functional test bench. |
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It has very efficient hardware. |
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8 symbol (64 bits) error-correcting capability |
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Customization on request |
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Continuous high speed decoding algorithm |
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Low gate count |